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august 17, 2005 ? cypress semiconductor corp. 2005 ? document no. 38-12036 rev. *a 1 cypress semiconductor preliminary data sheet cy8c9520, cy8c9540, and cy8c9560 20-, 40-, and 60-bit i/o expander with eeprom features i2c? interface logic electrically compatible with smbus. up to 20 (cy8c9520), 40 (cy8c9540) or 60 (cy8c9560) i/o data pins independently configurable as inputs, outputs, bi-directional input/outputs or pwm outputs. 4/8/16 pwm sources with 8-bit resolution. extendable soft addressing? algorithm allowing flexible i2c-address configuration. internal 3-/11-/27-kbyte eeprom. storage of user defaults and i/o port settings in the internal eeprom. optional eeprom write disable (wd) input. interrupt output indicates input pin level changes and pulse width modulator (pwm) state changes. internal power-on reset (por). figure 1-1. top level block diagram overview the cy8c95xx is a multi-port i/o expander with on-board user- available eeprom and several pwm outputs. all devices in this family operate identically but differ in i/o pins, number of pwms, and internal eeprom size. the cy8c95xx operates as two i2c slave devices. the first device is a multi-port i/o expander (single i2c address to access all ports via registers). the second device is a serial eeprom. dedicated configuration registers can be used to dis- able the eeprom. the eeprom utilizes 2-byte addressing to support the 28-kbyte eeprom address space. the selected device is defined by the most significant bits of the i2c address or by specific register addressing. the i/o expander's data pins can be independently assigned as inputs, outputs, quasi-bidirectional input/outputs or pwm ouputs. the individual data pins can be configured as open drain/collector, strong drive (10 ma source, 25 ma sink), resis- tively pulled-up/-down, or high-impedance. the factory default configuration is pulled-up internally. the system master writes to the i/o configuration registers via the i2c bus. configuration and output register settings can be stored as user defaults in a dedicated section of the eeprom. if user defaults have been stored in eeprom, they are restored to the ports at power-up. while this device can share the bus with smbus devices, it can only communicate with i2c-masters. there is one dedicated pin that is configured as an interrupt out- put (int) and can be connected to the interrupt logic of the sys- tem master. this signal can inform the system master that there is incoming data on its ports or that the pwm output state was changed. the eeprom is byte-readable and supports byte-by-byte writ- ing. a pin can be configured as an eeprom write disable (wd) input that blocks write operations when set high. the con- figuration registers can also disable eeprom operations. the cy8c95xx has one fixed address pin (a0) and up to six additional pins (a1-a6) which allow up to 128 devices to share a common two-wire i2c data bus. the extendable soft address- ing algorithm provides the option to choose the number of pins needed to assign the desired address. pins not used for address bits are available as gpio pins. eeprom us er settings area us er available area control unit gport 0 gport 1 gport 2 gport 3 gport 7 pwm 0 pwm 15 power-on-reset 1.5 mhz 93.75 khz divider (1-255) clocks 32 khz 24 mhz wd scl sda v dd v ss 8 bit i/o 5 bit i/o 3 bit i/o or a4-a 6 4 bit i/o or a1-a 3, w 8 bit i/o 8 bit i/o int a0
august 17, 2005 document no. 38-12036 rev. *a 2 cy8c95xx preliminary data sheet overview there are 4 (cy8c9520), 8 (cy8c9540) or 16 (cy8c9560) independently configurable 8-bit pwms. these pwms are denoted as pwm0-pwm15. each pwm can be clocked by one of six available clock sources. architecture the figure titled ?top level block diagram? on page 1 illustrates the device block diagram. the main blocks include the control unit, pwms, eeprom and i/o ports. the control unit executes commands received from the i2c bus and transfers data between other bus devices and the master device. the on-chip eeprom can be separated conventionally into two regions. the first region is designed to store data and is avail- able for byte-wide read/writes via the i2c bus. it is possible to prevent write operations by setting the wd pin to high. all eeprom operations can be blocked by configuration register settings. the second region allows the user to store the port and pwm default settings using special commands. these defaults will be automatically reloaded and processed after device power-on. the number of i/o lines and pwm sources is presented in the following table. there are four pins on gport 2 and three on gport 1 that can be used as general purpose i/o or eeprom write disable (wd) and i2c-address input (a1-a6), depending on configuration set- tings. the figure titled ?logical structure of the i/o port? shows the single port logical structure. the port drive mode register gives the option to select one of seven available modes for each pin separately: pulled-up/-down, open drain high/low, strong drive fast/slow, or high-impedance. by default these configuration registers store values setting i/o pins to pulled-up. the invert register allows for inversion of the logic of the input registers separately for each pin. the select pwm register allows pins to be assigned as pwm outputs. all of these configuration regis- ters are read/writable using corresponding commands in the multi-port device. figure 1-2. logical structure of the i/o port the port input and output registers are separated. when the output register is written, the data is sent to the external pins. when the input register is read, the external pin logic levels are captured and transferred. as a result, the read data can be dif- ferent from written output register data. this allows for imple- mentation of a quasi-bidirectional input-output mode, when the corresponding binary digit is configured as pulled-up/down out- put. each gport has an interrupt mask register and an interrupt sta- tus register. each high bit in the interrupt status register signals that there has been a change in the corresponding input line since the last read of that interrupt status register. the interrupt status register is cleared after each read. the interrupt mask register enables/disables activation of the int line when input levels are changed. each high in the interrupt mask register masks (disables) an interrupt generated from the corresponding input line. applications each gpio pin can be used to monitor and control various board-level devices, including leds and system intrusion detection devices. the on-board eeprom can be used to store information such as error codes or board manufacturing data for read-back by application software for diagnostic purposes. table 1-1. gpio availability port cy8c9520 cy8c9540 cy8c9560 gport 0 8 bit 8 bit 8 bit gport 1 5-8 bit ? 5-8 ? bit 5-8 bit ? gport 2 0-4 bit ? 0-4 ? bit 0-4 bit ? gport 3 - 8 bit 8 bit gport 4 - 8 bit 8 bit gport 5 - 4 bit 8 bit gport 6 - - 8 bit gport 7 - - 8 bit pwms 4 8 16 * this port contains configuration-dependant gpio lines or a1-a6 and wd lines. gportx 7 drive mode registers drive mode pull-up drive mode high-z interrupt status interrupt mask pin direction inversion input register select pwm output register 8 bit i/o data pwms
august 17, 2005 document no. 38-12036 rev. *a 3 cy8c95xx preliminary data sheet overview device access addressing following a start condition, the i2c master device sends a byte to address an i2c slave. this address selects the device to be accessed in the cy8c95xx. by default there are two possible address formats in binary representation: 010000a0x and 101000a0x. the first is used to access the multi-port device and the second to access the eeprom. if additional address lines (a1-a6) are used then the device addressing table 1-2 defines the device addresses. this addressing method uses a technique called extendable soft addressing?, described later in this document. when all address lines a1-a6 are used, the device being accessed is defined by the first byte following the address in the write transaction. if the most significant bit (msb) of this byte is ?0?, this byte is treated as a command (register address) byte of the multi-port device. if the msb is ?1?, this byte is the first of a 2- byte eeprom address. in this case, the device will mask the msb to determine the eeprom address. serial eeprom device eeprom reading and writing operations require 2 bytes, ahi and alo, which indicate which memory address to use. to read one or more bytes, the master device addresses the unit with a write cycle (= 0) to send ahi followed by alo, read- dresses the unit with a read cycle (= 1), and reads one or more data bytes. each data byte read will increment the internal address counter by one up to the end of the eeprom address space. a read or write beyond the end of the eeprom address space should result in a nak response by the port expander. to write data to the eeprom, the master device performs one write cycle, with the first two bytes being ahi followed by alo. this is followed by one or more data bytes. in the case of block writing it is advisable to set the starting address on the begin- ning of the 64-byte boundary, for example 01c0h or 0080h, but this is not mandatory. when a 64-byte boundary is crossed in the eeprom, the i2c clock is stretched while the device per- forms an eeprom write sequence. if the end of available eeprom space is reached, then further writes will be responded to with a nak. refer to figure 2-2, ?memory reading and writing,? on page 10 , which illustrates memory reading and writing proce- dures for the eeprom device. multi-port i/o device this device allows the user to set various configurations and i/o operations through internal registers. each data transfer is preceded by the command byte. this byte is used as a pointer to a register that will receive or transmit data. available registers are listed in table 3-1, ?the device register address map,? on page 11 . table 1-2. device addressing multi-port device eeprom device 01 0 0 0 0 a 0 r/w 10 1 00 0a 0 r/w 01000a 1 a 0 r/w 10 1 00a 1 a 0 r/w 0100a 2 a 1 a 0 r/w 10 1 0a 2 a 1 a 0 r/w 010a 3 a 2 a 1 a 0 r/w 10 1a 3 a 2 a 1 a 0 r/w 01a 4 a 3 a 2 a 1 a 0 r/w 10a 4 a 3 a 2 a 1 a 0 r/w 0a 5 a 4 a 3 a 2 a 1 a 0 r/w 1a 5 a 4 a 3 a 2 a 1 a 0 r/w a 6 a 5 a 4 a 3 a 2 a 1 a 0 r/w a 6 a 5 a 4 a 3 a 2 a 1 a 0 r/w
august 17, 2005 document no. 38-12036 rev. *a 4 cy8c95xx preliminary data sheet overview document conventions acronyms the following table lists the acronyms that are used in this doc- ument. units of measure a units of measure table is located in the electrical specifica- tions section. table 4-1, ?units of measure,? on page 16 lists all the abbreviations used in section 4. numeric naming hexidecimal numbers are represented with all letters in upper- case with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexidecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an ap- pended lowercase ?b? (e.g., 01010100b? or ?01000011b?). num- bers not indicated by an ?h?, ?b?, or 0x are decimal. table of contents the following is a table of contents for the remainder of this data sheet. 2. pinouts and pin descriptions ..................................................5 2.1 pinouts ..............................................................................5 2.1.1 28-pin part pinout ................................................5 2.1.2 48-pin part pinout ................................................6 2.1.3 100-pin part pinout ..............................................7 2.2 pin descriptions ................................................................9 2.2.1 extendable soft addressing? .............................9 2.2.2 interrupt pin (int) .................................................9 2.2.3 write disable pin (wd) ........................................9 2.2.4 external reset pin (xres) ..................................9 2.2.5 working with pwms .............................................9 3. register reference .................................................................11 3.1 register mapping table ..................................................11 3.2 register descriptions ......................................................12 3.2.1 input port registers (00h - 07h) .........................12 3.2.2 output port registers (08h - 0fh) ......................12 3.2.3 int. status port registers (10h - 17h) .................12 3.2.4 port select register (18h) ..................................12 3.2.5 interrupt mask port register (19h) .....................12 3.2.6 select pwm register (1ah) ...............................12 3.2.7 inversion register (1bh) .....................................12 3.2.8 port direction register (1ch) .............................12 3.2.9 drive mode registers (1dh-23h) ........................13 3.2.10 pwm select register (28h) ................................13 3.2.11 config (29h) ........................................................13 3.2.12 period register (2ah) .........................................13 3.2.13 pulse width register (2bh) ................................13 3.2.14 divider register (2ch) ........................................13 3.2.15 enable register (2dh) ........................................13 3.2.16 device id/status register (2eh) ........................14 3.2.17 command register (30h) ...................................14 3.3 commands description ...................................................14 3.3.1 store config to e2 por defaults cmd (01h) .....14 3.3.2 restore factory defaults cmd (02h) ..................14 3.3.3 write e2 por defaults cmd (03h) .....................14 3.3.4 read e2 por defaults cmd (04h) ....................15 3.3.5 write device config cmd (05h) ..........................15 3.3.6 read device config cmd (06h) .........................15 3.3.7 reconfigure device cmd (07h) ..........................15 4. electrical specifications .........................................................16 4.1 absolute maximum ratings .............................................16 4.2 operating temperature ...................................................17 4.3 dc electrical characteristics ...........................................17 4.3.1 dc chip-level specifications .............................17 4.3.2 dc programming specifications ........................18 4.3.3 dc general purpose i/o specifications .............18 4.4 ac electrical characteristics ...........................................19 4.4.1 ac general purpose i/o specifications .............19 4.4.2 ac pwm output jitter specifications .................19 4.4.3 ac i2c specifications .........................................20 5. packaging information ...........................................................21 5.1 packaging dimensions ....................................................21 5.2 thermal impedances .......................................................23 5.3 solder reflow peak temperature ...................................23 6. ordering information ..............................................................24 6.1 ordering code definitions ...............................................24 7. sales and service information ...............................................25 7.1 revision history ..............................................................25 7.2 copyrights and code protection .....................................25 acronym description ac alternating current dc direct current eeprom electrically erasable programmable read-only memory (e 2 ) gpio general purpose io i/o input/output msb most-significant bit por power on reset pwm pulse width modulator
august 17, 2005 document no. 38-12036 rev. *a 5 2. pinouts and pin descriptions this chapter describes, lists, and illustrates the cy8c95xx device pins and pinout configurations, along with application examp les. 2.1 pinouts the cy8c95xx device is available in a variety of packages, which are listed and illustrated in the following tables. 2.1.1 28-pin part pinout table 2-1. 28-pin part pinout (ssop) pin no. pin name description cy8c9520 28-pin device 1 gport0_bit0_pwm3 port 0, bit 0, pwm 3. 2 gport0_bit1_pwm1 port 0, bit 1, pwm 1. 3 gport0_bit2_pwm3 port 0, bit 2, pwm 3. 4 gport0_bit3_pwm1 port 0, bit 3, pwm 1. 5 gport0_bit4_pwm3 port 0, bit 4, pwm 3. 6 gport0_bit5_pwm1 port 0, bit 5, pwm 1. 7 gport0_bit6_pwm3 port 0, bit 6, pwm 3. 8 gport0_bit7_pwm1 port 0, bit 7, pwm 1. 9v ss ground connection. 10 i 2 c serial clock (scl) i 2 c clock. 11 i 2 c serial data (sda) i 2 c data. 12 gport2_bit3_pwm3/a1 port 2, bit 3, pwm 3, address 1. 13 a0 address 0. 14 v ss ground connection. 15 gport2_bit2_pwm0/wd port 2, bit 2, pwm 0, e 2 write disable. 16 int 17 gport2_bit1_pwm0/a2 port 2, bit 1, pwm 0, address 2. 18 gport2_bit0_pwm2/a3 port 2, bit 0, pwm 2, address 3. 19 xres active high external reset with internal pull down. 20 gport1_bit7_pwm0/a4 port 1, bit 7, pwm 0, address 4. 21 gport1_bit6_pwm2/a5 port 1, bit 6, pwm 2, address 5. 22 gport1_bit5_pwm0/a6 port 1, bit 5, pwm 0, address 6. 23 gport1_bit4_pwm2 port 1, bit 4, pwm 2. 24 gport1_bit3_pwm0 port 1, bit 3, pwm 0. 25 gport1_bit2_pwm2 port 1, bit 2, pwm 2. 26 gport1_bit1_pwm0 port 1, bit 1, pwm 0. 27 gport1_bit0_pwm2 port 1, bit 0, pwm 2. 28 v dd supply voltage. gport0_bit0_pwm3 gport0_bit1_pwm1 gport0_bit2_pwm3 gport0_bit3_pwm1 gport0_bit4_pwm3 gport0_bit5_pwm1 gport0_bit6_pwm3 gport0_bit7_pwm1 vss i2c serial cl ock (scl) i2c serial clock (sda) gport2_bit3_pwm3/a1 a0 vss vdd gport1_bit0_pwm2 gport1_bit1_pwm0 gport1_bit2_pwm2 gport1_bit3_pwm0 gport1_bit4_pwm2 gport1_bit5_pwm0/a6 gport1_bit6_pwm2/a5 gport1_bit7_pwm0/a4 xres gport2_bit0_pwm2/a3 gport2_bit1_pwm0/a2 int gport2_bit2_pwm0/wd ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
august 17, 2005 document no. 38-12036 rev. *a 6 cy8c95xx preliminary data sheet 2. pinouts and pin descriptions 2.1.2 48-pin part pinout table 2-2. 48-pin part pinout (ssop) pin no. pin name description cy8c9540 48-pin device 1 gport0_bit0_pwm7 port 0, bit 0, pwm 7. 2 gport0_bit1_pwm5 port 0, bit 1, pwm 5. 3 gport0_bit2_pwm3 port 0, bit 2, pwm 3. 4 gport0_bit3_pwm1 port 0, bit 3, pwm 1. 5 gport0_bit4_pwm7 port 0, bit 4, pwm 7. 6 gport0_bit5_pwm5 port 0, bit 5, pwm 5. 7 gport0_bit6_pwm3 port 0, bit 6, pwm 3. 8 gport0_bit7_pwm1 port 0, bit 7, pwm 1. 9 gport3_bit0_pwm7 port 3, bit 0, pwm 7. 10 gport3_bit1_pwm5 port 3, bit 1, pwm 5. 11 gport3_bit2_pwm3 port 3, bit 2, pwm 3. 12 gport3_bit3_pwm1 port 3, bit 3, pwm 1. 13 v ss ground connection. 14 gport3_bit4_pwm7 port 3, bit 4, pwm 7. 15 gport3_bit5_pwm5 port 3, bit 5, pwm 5. 16 gport3_bit6_pwm3 port 3, bit 6, pwm 3. 17 gport3_bit7_pwm1 port 3, bit 7, pwm 1. 18 gport5_bit2_pwm3 port 5, bit 2, pwm 3. 19 gport5_bit3_pwm1 port 5, bit 3, pwm 1. 20 i 2 c serial clock (scl) i 2 c clock. 21 i 2 c serial data (sda) i 2 c data. 22 gport2_bit3_pwm3/a1 port 2, bit 3, pwm 3, address 1. 23 a0 address 0. 24 v ss ground connection. 25 gport2_bit2_pwm0/wd port 2, bit 2, pwm 0, e 2 write disable. 26 int 27 gport2_bit1_pwm4/a2 port 2, bit 1, pwm 4, address 2. 28 gport2_bit0_pwm6/a3 port 2, bit 0, pwm 6, address 3. 29 gport5_bit1_pwm0 port 5, bit 1, pwm 0. 30 gport5_bit0_pwm2 port 5, bit 0, pwm 2. 31 gport4_bit7_pwm0 port 4, bit 7, pwm 0. 32 gport4_bit6_pwm2 port 4, bit 6, pwm 2. 33 gport4_bit5_pwm4 port 4, bit 5, pwm 4. 34 gport4_bit4_pwm6 port 4, bit 4, pwm 6. 35 xres active high external reset with internal pull down. 36 gport4_bit3_pwm0 port 4, bit 3, pwm 0. 37 gport4_bit2_pwm2 port 4, bit 2, pwm 2. 38 gport4_bit1_pwm4 port 4, bit 1, pwm 4. 39 gport4_bit0_pwm6 port 4, bit 0, pwm 6. 40 gport1_bit7_pwm0/a4 port 1, bit 7, pwm 0, address 4. 41 gport1_bit6_pwm2/a5 port 1, bit 6, pwm 2, address 5. 42 gport1_bit5_pwm4/a6 port 1, bit 5, pwm 4, address 6. 43 gport1_bit4_pwm6 port 1, bit 4, pwm 6. 44 gport1_bit3_pwm0 port 1, bit 3, pwm 0. 45 gport1_bit2_pwm2 port 1, bit 2, pwm 2. 46 gport1_bit1_pwm4 port 1, bit 1, pwm 4. 47 gport1_bit0_pwm6 port 1, bit 0, pwm 6. 48 v dd supply voltage. ssop gport0_bit0_pwm7 vdd gport0_bit1_pwm5 gport1_bit0_pwm6 gport0_bit2_pwm3 gport1_bit1_pwm4 gport0_bit3_pwm1 gport1_bit2_pwm2 gport0_bit4_pwm7 gport1_bit3_pwm0 gport0_bit5_pwm5 gport1_bit4_pwm6 gport0_bit6_pwm3 gport1_bit5_pwm4/a6 gport0_bit7_pwm1 gport1_bit6_pwm2/a5 gport3_bit0_pwm7 gport1_bit7_pwm0/a4 gport3_bit1_pwm5 gport4_bit0_pwm6 gport3_bit2_pwm3 gport4_bit1_pwm4 gport3_bit3_pwm1 gport4_bit2_pwm2 vss gport4_bit3_pwm0 gport3_bit4_pwm7 xr e s gport3_bit5_pwm5 gport4_bit4_pwm6 gport3_bit6_pwm3 gport4_bit5_pwm4 gport3_bit7_pwm1 gport4_bit6_pwm2 gport5_bit2_pwm3 gport4_bit7_pwm0 gport5_bit3_pwm1 gport5_bit0_pwm2 i2c serial clock (scl) gport5_bit1_pwm0 i2c serial data (sda) gport2_bit0_pwm6/a3 gport2_bit3_pwm3/a1 gport2_bit1_pwm4/a2 a0 int vss gport2_bit2_pwm0/wd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 43 44 42 40 41 39 38 37 36 35 33 34 32 31 30 29 28 27 26 25
august 17, 2005 document no. 38-12036 rev. *a 7 cy8c95xx preliminary data sheet 2. pinouts and pin descriptions 2.1.3 100-pin part pinout table 2-3. 100-pin part pinout (tqfp) pin no. name description pin no. name description 1 dnu dnu = do not use; leave floating. 51 dnu dnu = do not use; leave floating. 2 dnu dnu = do not use; leave floating. 52 gport5_bit1_pwm8 port 5, bit 1, pwm 8. 3 gport0_bit3_pwm1 port 0, bit 3, pwm 1. 53 gport5_bit0_pwm10 port 5, bit 0, pwm 10. 4 gport0_bit4_pwm7 port 0, bit 4, pwm 7. 54 gport5_bit4_pwm12 port 5, bit 4, pwm 12. 5 gport0_bit5_pwm5 port 0, bit 5, pwm 5. 55 gport5_bit5_pwm14 port 5, bit 5, pwm 14. 6 gport0_bit6_pwm3 port 0, bit 6, pwm 3. 56 gport4_bit7_pwm8 port 4, bit 7, pwm 8. 7 gport0_bit7_pwm1 port 0, bit 7, pwm 1. 57 gport4_bit6_pwm10 port 4, bit 6, pwm 10. 8 gport3_bit0_pwm7 port 3, bit 0, pwm 7. 58 gport4_bit5_pwm12 port 4, bit 5, pwm 12. 9 gport3_bit1_pwm5 port 3, bit 1, pwm 5. 59 gport4_bit4_pwm14 port 4, bit 4, pwm 14. 10 gport3_bit2_pwm3 port 3, bit 2, pwm 3. 60 dnu dnu = do not use; leave floating. 11 gport3_bit3_pwm1 port 3, bit 3, pwm 1. 61 dnu dnu = do not use; leave floating. 12 dnu dnu = do not use; leave floating. 62 xres active high external reset with internal pull down. 13 dnu dnu = do not use; leave floating. 63 gport4_bit3_pwm0 port 4, bit 3, pwm 0. 14 dnu dnu = do not use; leave floating. 64 gport4_bit2_pwm2 port 4, bit 2, pwm 2. 15 v ss ground connection. 65 v ss ground connection. 16 gport3_bit4_pwm15 port 3, bit 4, pwm 157. 66 gport4_bit1_pwm4 port 4, bit 1, pwm 4. 17 gport3_bit5_pwm13 port 3, bit 5, pwm 13. 67 gport4_bit0_pwm6 port 4, bit 0, pwm 6. 18 gport3_bit6_pwm11 port 3, bit 6, pwm 11. 68 gport1_bit7_pwm0/a4 port 1, bit 7, pwm 0, address 4. 19 gport3_bit7_pwm9 port 3, bit 7, pwm 9. 69 gport1_bit6_pwm2/a5 port 1, bit 6, pwm 2, address 5. 20 gport5_bit7_pwm15 port 5, bit 7, pwm 15. 70 gport1_bit5_pwm4/a6 port 1, bit 5, pwm 4, address 6. 21 gport5_bit6_pwm13 port 5, bit 6, pwm 13. 71 dnu dnu = do not use; leave floating. 22 gport5_bit2_pwm11 port 5, bit 2, pwm 11. 72 gport1_bit4_pwm6 port 1, bit 4, pwm 6. 23 gport5_bit3_pwm9 port 5, bit 3, pwm 9. 73 dnu dnu = do not use; leave floating. 24 i 2 c serial clock (scl) i 2 c clock. 74 gport1_bit3_pwm0 port 1, bit 3, pwm 0. 25 dnu dnu = do not use; leave floating. 75 dnu dnu = do not use; leave floating. 26 dnu dnu = do not use; leave floating. 76 dnu dnu = do not use; leave floating. 27 dnu dnu = do not use; leave floating. 77 gport1_bit2_pwm2 port 1, bit 2, pwm 2. 28 i 2 c serial data (sda) i 2 c data. 78 dnu dnu = do not use; leave floating. 29 gport2_bit3_pwm11/a1 port 2, bit 3, pwm 11, address 1. 79 gport1_bit1_pwm4 port 1, bit 1, pwm 4. 30 a0 address 0. 80 dnu dnu = do not use; leave floating. 31 dnu dnu = do not use; leave floating. 81 gport1_bit0_pwm6 port 1, bit 0, pwm 6. 32 v dd supply voltage. 82 v dd supply voltage. 33 dnu dnu = do not use; leave floating. 83 v dd supply voltage. 34 v ss ground connection. 84 v ss ground connection. 35 dnu dnu = do not use; leave floating. 85 v ss ground connection. 36 gport7_bit7_pwm15 port 7, bit 7, pwm 15. 86 gport6_bit0_pwm0 port 6, bit 0, pwm 0. 37 gport7_bit6_pwm14 port 7, bit 6, pwm 14. 87 gport6_bit1_pwm1 port 6, bit 1, pwm 1. 38 gport7_bit5_pwm13 port 7, bit 5, pwm 13. 88 gport6_bit2_pwm2 port 6, bit 2, pwm 2. 39 gport7_bit4_pwm12 port 7, bit 4, pwm 12. 89 gport6_bit3_pwm3 port 6, bit 3, pwm 3. 40 gport7_bit3_pwm11 port 7, bit 3, pwm 11. 90 gport6_bit4_pwm4 port 6, bit 4, pwm 4. 41 gport7_bit2_pwm10 port 7, bit 2, pwm 10. 91 gport6_bit5_pwm5 port 6, bit 5, pwm 5. 42 gport7_bit1_pwm9 port 7, bit 1, pwm 9. 92 gport6_bit6_pwm6 port 6, bit 6, pwm 6. 43 gport7_bit0_pwm8 port 7, bit 0, pwm 8. 93 gport6_bit7_pwm7 port 6, bit 7, pwm 7. 44 gport2_bit2_pwm8/wd port 2, bit 2, pwm 8, e 2 write disable. 94 dnu dnu = do not use; leave floating. 45 int 95 gport0_bit0_pwm7 port 0, bit 0, pwm 7. 46 gport2_bit1_pwm12/a2 port 7, bit 7, pwm 0, address 4. 96 dnu dnu = do not use; leave floating. 47 gport2_bit0_pwm14/a3 port 7, bit 6, pwm 2, address 5. 97 gport0_bit1_pwm5 port 0, bit 1, pwm 5. 48 dnu dnu = do not use; leave floating. 98 dnu dnu = do not use; leave floating. 49 dnu dnu = do not use; leave floating. 99 gport0_bit2_pwm3 port 0, bit 2, pwm 3. 50 dnu dnu = do not use; leave floating. 100 dnu dnu = do not use; leave floating.
august 17, 2005 document no. 38-12036 rev. *a 8 cy8c95xx preliminary data sheet 2. pinouts and pin descriptions cy8c9560 100-pin device a.) dnu = do not use; leave floating. tqfp dnu a dnu gport0_bit3_pwm1 gport0_bit4_pwm7 gport0_bit5_pwm5 gport0_bit6_pwm3 gport0_bit7_pwm1 gport3_bit0_pwm7 gport3_bit1_pwm5 gport3_bit2_pwm3 gport3_bit3_pwm1 dnu dnu dnu vss gport3_bit4_pwm15 gport3_bit5_pwm13 gport3_bit6_pwm11 gport3_bit7_pwm9 gport5_bit7_pwm15 gport5_bit6_pwm13 gport5_bit2_pwm11 gport5_bit3_pwm9 i2c serial clock (scl) dnu dnu vss gport7_bit3_pwm11 gport2_bit1_pwm12/a2 dnu i2c serial data (sda) gport2_bit3_pwm11/a1 a0 dnu vdd dnu dnu gport7_bit7_pwm15 gport7_bit6_pwm14 gport7_bit5_pwm13 gport7_bit4_pwm12 gport7_bit2_pwm10 gport7_bit1_pwm9 gport7_bit0_pwm8 gport2_bit2_pwm8/wd int gport2_bit0_pwm14/a3 dnu dnu dnu dnu gport1_bit3_pwm0 dnu gport1_bit4_pwm6 dnu gport1_bit5_pwm4/a 6 gport1_bit6_pwm2/a 5 gport1_bit7_pwm0/a 4 gport4_bit0_pwm6 gport4_bit1_pwm4 vss gport4_bit2_pwm2 gport4_bit3_pwm0 xr e s dnu dnu gport4_bit4_pwm14 gport4_bit5_pwm12 gport4_bit6_pwm10 gport4_bit7_pwm8 gport5_bit5_pwm14 gport5_bit4_pwm12 gport5_bit0_pwm10 gport5_bit1_pwm8 dnu dnu gport0_bit2_pwm3 dnu gport0_bit1_pwm5 dnu gport0_bit0_pwm7 dnu gport6_bit7_pwm7 gport6_bit6_pwm6 gport6_bit5_pwm5 gport6_bit4_pwm4 gport6_bit3_pwm3 gport6_bit2_pwm2 gport6_bit1_pwm1 gport6_bit0_pwm0 vss vss vdd vdd gport1_bit0_pwm6 dnu gport1_bit1_pwm4 dnu gport1_bit2_pwm2 dnu 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 50 49
august 17, 2005 document no. 38-12036 rev. *a 9 cy8c95xx preliminary data sheet 2. pinouts and pin descriptions 2.2 pin descriptions 2.2.1 extendable soft addressing? the a0 line is always used to define the corresponding bit of the i2c address. this pin should be pulled up or down. if a0 is a strong pull-up or a strong pull-down (wired through 330 or less resistor to vdd or vss), then that is the only address line being specified and the a1-a6 lines are used as gpio. if a0 is a weak pull-up or a weak pull-down (connected to vdd or vss through 75k- 200k-ohm resistor), then a0 is not the only externally defined address bit. there is a pin assigned to be a1 if it is needed. this pin can be pulled-up or pulled-down strong or weak with a resistor. as with a0, the type of pull determines whether the address bit is the last externally defined address bit. differently from a0, a1 is not dedicated as an address pin. it is only used if a0 is not the only address bit externally defined. there are also predefined pins for a2, a3, a4, a5 and a6 that will only be used for addressing if needed. the last address bit in the chain is pulled strong. that way, only the number of pins needed to assign the address desired for the part are allocated as address pins, any pins not used for address bits are avail- able to be used as gpio pins. the table , ?device addressing,? on page 3 defines the resulting device i2c address. 2.2.2 interrupt pin (int) the interrupt output (if enabled) is activated if one of the follow- ing events occurs: one of the gpio port pins changes state and the corresponding bit in the interrupt mask register is set low. when a pwm driven by the slowes t clock source (367.6 hz) and assigned to a pin changes state and the pin?s corresponding bit in the interrupt mask register is set low. the interrupt line is deactivated when the master device per- forms a read from the corresponding interrupt status register. 2.2.3 write disable pin (wd) if this feature is enabled, ?0? allows writes to the eeprom and ?1? blocks any memory writes. this pin is checked immediately before performing any write to memory. if the eee bit in the enable register is not set (eeprom disabled) or bit eero is set (eeprom is read-only) then wd line level is ignored. note that ?1? on this line blocks all commands which perform operations with eeprom (see table 3-9, ?available com- mands,? on page 14 ). this line may be enabled/disabled by bit 1 of the enable regis- ter (2dh): ?1? enables wd function, ?0? disables. 2.2.4 external reset pin (xres) a full device reset is caused by pulling the xres pin high. the xres pin has an always-on pull-down resistor, so it does not require an external pull down for operation. it can be tied directly to ground or left open. behavior after xres is similar to por. 2.2.5 working with pwms there are four independent pwms in the cy8c9520, eight in the cy8c9540 and sixteen in the cy8c9560. each i/o pin can be configured as a pwm output by writing ?1? to the correspond- ing bit of the select pwm register (see table 3-2, ?output and select pwm registers logic,? on page 127 ). the next step of pwm configuration is clock source selection using the config pwm registers. there are six available clock sources: 32 khz (default), 24 mhz, 1.5 mhz, 93.75 khz, 367.6 hz or previous pwm output. (see figure 2-1). figure 2-1. clock sources by default, 32 khz is selected as the pwm clock. pwm period registers are used to set the output period: equation 1 allowed values are between 1 and ffh. the pwm pulse width register sets the duration of the pwm output pulse. allowed values are between zero and the (period- 1) value. the duty cycle ratio can be computed using the follow- ing equation: equation 2 di vi der (1-255) 93.75 khz 367.6 hz - 93.75 khz 1.5 mhz 24 mhz 32 khz t out period t cl k = d utycycle pulsewidth period --------------------------- --- =
august 17, 2005 document no. 38-12036 rev. *a 10 cy8c95xx preliminary data sheet 2. pinouts and pin descriptions figure 2-2. memory reading and writing figure 2-3. port reading and writing in multi-port device s a6 a5 a3 a2 a1 a0 1 a a4 data(addr) a data(addr+1) ack from slave s a6 a5 a3 a2 a1 a0 0 a high(addr) a low(addr) a4 a n p no ack from master stop a ... ack from master ack from master ack from slave ack from slave ack from slave r/w start slave address r/w memory address reading from eeprom data 1 s a6 a5 a3 a2 a1 a0 0 a high(addr) a low(addr) a4 a ack from slave ack from slave ack from slave start slave address r/w memory address writing to eeprom a data 2 a p if current address crosses 64-byte block boundary, then device performs real writing to eeprom stop a ... up to the end of address space s 0 a data from gport1 ... start slave address r/w register address = 1 reading from gport 1 0 0 0 0 0 0 0 1 a s a6 a5 a3 a2 a1 a0 a4 a6 a5 a3 a2 a1 a0 a4 1 a a data from gport 2 a n p no ack from master stop ack from slave ack from slave ack from master r/w at this moment, device performs reading from gport 1 reading from gport 2 s 0 a data from gport1 ... start slave address r/w register address = 09h writing from gport 1 0 0 0 0 1 0 0 1 a a6 a5 a3 a2 a1 a0 a4 a a ack from slave ack from slave ack from slave at this moment, device performs output to gport 1 data from gport 2 data from gport 0 output to gport 2 output to gport 3 a ack from slave p stop
august 17, 2005 document no. 38-12036 rev. *a 11 3. register reference this chapter lists and describes the registers of the cy8c95xx device, starting with a register map and then detailed descripti ons of register types. 3.1 register mapping table the register address is auto-incrementing. if the master device writes or reads data to or from one register and then continues data transfer in the same i2c transaction, sequential bytes will be written or read to or from the following registers. for exam- ple, if the first byte is sent to the output port 1 register, then the next bytes will be written to output port 2, output port 3, output port 4 etc. the first byte of each write transaction is treated as the register address. to read data from a seires of registers, the master device should write the starting register address byte then perform a start and series of read transactions. if no address was sent, reads start from address 0. to read a specific register address, the master device should write the register address byte, then perform a start and read transaction. see figure 1-3, ?port reading and writing in multi-port device,? on page 11. the device?s register mapping is listed in table 3-1. table 3-1. the device register address map address register default register value 00h input port 0 none 01h input port 1 none 02h input port 2 none 03h input port 3 none 04h input port 4 none 05h input port 5 none 06h input port 6 none 07h input port 7 none 08h output port 0 ffh 09h output port 1 ffh 0ah output port 2 ffh 0bh output port 3 ffh 0ch output port 4 ffh 0dh output port 5 ffh 0eh output port 6 ffh 0fh output port 7 ffh 10h interrupt status port 0 00h 11h interrupt status port 1 00h 12h interrupt status port 2 00h 13h interrupt status port 3 00h 14h interrupt status port 4 00h 15h interrupt status port 5 00h 16h interrupt status port 6 00h 17h interrupt status port 7 00h 18h port select 00h 19h interrupt mask ffh 1ah select pwm for port output 00h 1bh inversion 00h 1ch pin direction - input/output 00h 1dh drive mode - pull up ffh 1eh drive mode - pull down 00h 1fh drive mode - open drain high 00h 20h drive mode - open drain low 00h 21h drive mode - strong 00h 22h drive mode - slow strong 00h 23h drive mode - high-z 00h 24h reserved none 25h reserved none 26h reserved none 27h reserved none 28h pwm select 00h 29h config pwm 00h 2ah period pwm ffh 2bh pulse width pwm 80h 2ch programmable divider ffh 2dh enable wde, eee, eero 00h 2eh device id/status 20h/40h/60h 2fh reserved none 30h command 00h table 3-1. the device register address map (continued) address register default register value
august 17, 2005 document no. 38-12036 rev. *a 12 cy8c95xx preliminary data sheet 3. register reference 3.2 register descriptions the registers for the cy8c95xx are described in the sections that follow. note that the pwm registers are located at addresses 28h to 2bh. 3.2.1 input port registers (00h - 07h) these registers represent actual logical levels on the pins and are used for i/o port reading operations. they are read-only. the inversion registers will change the state of reads to these ports. 3.2.2 output port registers (08h - 0fh) these registers are used for writing data to gpio ports. by default, all ports are in the pull-up mode allowing quasi-bidirec- tional i/o. to allow input operations without reconfiguration, these registers have to store ?1?s. output register data also affects pin states when pwms are enabled. see table 3-2. output and select pwm registers logic for details. figure 2-3 on page 10 illustrates port read/write procedures. the inversion registers have no effect on these ports. 3.2.3 int. status port registers (10h - 17h) each ?1? bit in these registers signals that there has been a change in the corresponding input line since the last read of that interrupt status register. each interrupt (int.) status register is cleared only after a read of that register. if a pwm is assigned to a pin, then all state changes of the pwm will set the corresponding bit in the interrupt status regis- ter. if the pin's interrupt mask is cleared and the pwm is set to the slowest possible rate allowed (driven by the programmable clock source with divide register 2dh set to ffh), then the int line will also be driven on the pwm state change. 3.2.4 port select register (18h) this register is used to select the gport to be configured. write a value of 0-7 to this register to select the port to program with the following registers, 19h-23h. 3.2.5 interrupt mask port register (19h) the interrupt mask register enables/disables activation of the int line when gpio input levels are changed. each ?1? in the interrupt mask register masks (disables) interrupts generated from the corresponding input line of the gport selected by the port select register (18h). 3.2.6 select pwm register (1ah) this register is used to allow each port to act as a pwm output. by default, all ports are configured as gpio lines. each ?1? in this register connects the corresponding pin of the gport selected by the port select register (18h) to the pwm output. output register data also affects the pin state when a pwm is enabled. see table 3-2 . note that a pin used as pwm output should be configured to the appropriate drive mode. see table 3-4 on page 13 for more information. table 3-2 describes the logic of the output and select pwm registers. 3.2.7 inversion register (1bh) this register can invert the logic of the input ports. each ?1? writ- ten to this register inverts the logic of the corresponding bit in the input register of the gport selected by the port select regis- ter (18h). the input registers' logic is presented in tab l e 3 - 3 . these registers have no effect on outputs or pwms. 3.2.8 port direction register (1ch) each bit in a port can be configured as either an input or an out- put. to perform this configuration, the port direction register (1ch) is used for the gport selected by the port select register (18h). if a bit in this register is set (written with '1'), the corre- sponding port pin is enabled as an input. if a bit in this register is cleared (written with '0'), the corresponding port pin is enabled as an output. table 3-2. output and select pwm registers logic output select pwm pin state 00 0 10 1 01 0 11current pwm table 3-3. inversion register logic pin state invert input 00 0 10 1 01 1 11 0
august 17, 2005 document no. 38-12036 rev. *a 13 cy8c95xx preliminary data sheet 3. register reference 3.2.9 drive mode registers (1dh-23h) each port's data pins can be set separately to one of seven available modes: pull-up/-down, open drain high/low, strong drive fast/slow, or high-impedance input. to perform this config- uration, the seven drive mode registers are used for the gport selected by the port select register (18h). each ?1? written to this register changes the corresponding line drive mode. regis- ters 1dh through 23h have last-register priority meaning that the bit set to high in which the last register was written will over- ride those that came before. reading these registers reflects the actual setting, not what was originally written. 3.2.10 pwm select register (28h) this register is used to select the pwm to be configured. write a value of 00h-0fh to this register to select the pwm to pro- gram with the following registers, 29h-2bh. 3.2.11 config (29h) this register is used to choose the clock source for the pwm selected by the pwm select register (28h) and interrupt logic. there are six available clock sources: 32 khz (default), 24 mhz, 1.5 mhz, 93.75 khz, 367.6 hz, or previous pwm output. the 367.6 hz clock is user programmable. it divides the 93.75 khz clock source by the divisor stored in the divider register (2ch). the default divide ratio is 255. (see tab l e 3 - 5 for details). by default, all pwms are clocked from 32 khz. each pwm can generate an interrupt at the rising or falling edge of the output pulse. there is a limitation on the clock source for a pwm to generate an interrupt. only the slowest speed source (programmed to 367.6 hz) with the divider equal to 255 allows interrupt generation. consequently, to create a pwm interrupt, it is necessary to choose the programmable divider output as the clock source (write xxxxx100b to config register (29h)), write 255 to the divide register (2ch), and select pwm for pin output (1ah). interrupt status is reflected in the interrupt status registers (10h- 17h) and can cause int line activation if enabled by the corre- sponding mask bit in the interrupt mask register: 3.2.12 period register (2ah) this register sets the period of the pwm counter. allowed val- ues are between 1 and ffh. the effective output waveform period of the pwm is: 3.2.13 pulse width register (2bh) this register sets the pulse width of the pwm output. allowed values are between zero and the (period - 1) value. the duty cycle ratio can be computed using the following equation: 3.2.14 divider register (2ch) this register sets the frequency on the output of the program- mable divider: allowed values are between 1 and 255. 3.2.15 enable register (2dh) the wde bit configures the write disable pin to operate either as a gpio or as wd. it also enables/disables eeprom opera- tions (eee bit) or makes the eeprom read-only (eero bit). bit assignments are shown in table 3-7 on page 14 . table 3-4. drive mode register settings register pin state description 1dh resistive pull up resistive high, strong low (default) 1eh resistive pull down strong high, resistive low 1fh open drain high slow strong high, high-z low 20h open drain low slow strong low, high-z high 21h strong drive strong high, strong low, fast output mode 22h slow strong drive strong high, strong low, slow output mode 23h high impedance high-z table 3-5. pwm clock sources config pwm pwm clock source xxxxx000b 32 khz (default) xxxxx001b 24 mhz xxxxx010b 1.5 mhz xxxxx011b 93.75 khz xxxxx100b 367.6 hz (programmable) xxxxx101b previous pwm table 3-6. period register config pwm pwm interrupt on xxxx0xxxb falling pulse edge (default) xxxx1xxxb rising pulse edge o ut clk t period t =? . p ulsewidth dutycycle period = 93.75 . k hz frequency d ivider =
august 17, 2005 document no. 38-12036 rev. *a 14 cy8c95xx preliminary data sheet 3. register reference each ?1? enables the corresponding feature, ?0? disables. writes to this register differ from other registers. the write sequence to modify the enable register is as follows: 1. send device i2c address with bit 0. 2. send register address 2dh. 3. send unlock key - the sequence of three bytes: 43h, 4dh, 53h; ('c', 'm', 's' in ascii bytes). 4. send new enable register value. this write sequence secures the register from accidental changes. the register can be read without the use of the unlock key. by default, eero and eeprom (eee bit) are disabled and wd line (wde bit) is set to gpio (wd disabled). when performing a burst write operation that crosses this regis- ter, the data written to this register will be ignored and the address will increment to 2eh. 3.2.16 device id/status register (2eh) this register stores device identifiers (2xh/4xh/6xh) and reflects which settings were loaded during startup, either factory defaults (fd) or user defaults (ud). by default during startup, the device will attempt to load the user default block. if it seems to be corrupted then factory defaults are loaded and the low nib- ble of this register is set high to inform which set is active. the high nibble is always equal to 2 for cy8c9520, 4 for cy8c9540, and 6 for cy8c9560. this register is read-only. 3.2.17 command register (30h) this register sends commands to the device, including current configuration as new por defaults, restore factory defaults, define por defaults, read por defaults, write device configura- tion, read device configuration, and reconfigure device with stored por defaults. the command set is presented in table 3- 9 . note that registers are not restored in parallel. do not assume any particular order to the restoration process. 3.3 commands description 3.3.1 store config to e 2 por defaults cmd (01h) the current ports settings (drive modes and output data) and other configuration registers are saved in the eeprom by using the store configuration command (cmd). these settings will be automatically loaded after the next device power-up or if the 07h command is issued. 3.3.2 restore factory defaults cmd (02h) this command replaces the saved user configuration with the factory default configuration. current settings are unaffected by this command. new settings will be loaded after the next device power-up or if the 07h command is issued. 3.3.3 write e 2 por defaults cmd (03h) this command is used to send new power-up defaults to the cy8c95xx without changing current settings unless the 07h command is issued afterwards. this command is followed by 147 data bytes according to ta b l e 3 - 1 0 . the crc is calculated as the xor of the 146 data bytes (00h-91h). if the crc check fails or an incomplete block is sent, then the slave will respond with a nak and the data will not be saved to eeprom. to define new por defaults the user must: write command 03h; write 146 data bytes with new values of registers; write 1 crc byte calculated as xor of previous 146 data bytes. content of the data block is described in tab le 3 -1 0 . table 3-7. enable register bit 7 6 5 4 3 2 1 0 function reserved eero eee wde default reserved 0 0 0 table 3-8. device id status register bit 7 8 5 4 3 2 1 0 function device family (2, 4,or 6) reserved fd/ud table 3-9. available commands command description 01h store device configuration to eeprom por defaults 02h restore factory defaults 03h write eeprom por defaults 04h read eeprom por defaults 05h write device configuration 06h read device configuration 07h reconfigure device with stored por defaults
august 17, 2005 document no. 38-12036 rev. *a 15 cy8c95xx preliminary data sheet 3. register reference 3.3.4 read e2 por defaults cmd (04h) this command is used to read the por settings stored in the eeprom. to read por defaults the user must: write command 04h; read 146 data bytes (see ta b l e 3 - 1 0 ). read 1 crc byte. 3.3.5 write device config cmd (05h) this command is used to send a new device configuration to the cy8c95xx. it is followed by 146 data bytes according to tab le 3 -1 0 . the crc is calculated as the xor of the 146 data bytes (00h-91h). if the crc check fails or an incomplete block is sent, then the slave will respond with a nak and the device will not use the data. this gives the user ?flat-address-space? access to all device settings. to set the current device configuration the user must: write command 05h; write 146 data bytes with new values of registers; write 1 crc byte calculated as xor of previous 146 data bytes. if the crc check passes, then the device will use the new set- tings immediately. content of the data block is described in tab le 3 -1 0 . 3.3.6 read device config cmd (06h) this command is used to read the current device configuration. it gives the user ?flat-address-space? access to all device set- tings. to read device configuration the user must: write command 06h; read 146 data bytes (see ta b l e 3 - 1 0 ). read 1 crc byte. 3.3.7 reconfigure device cmd (07h) this command is used to immediately reconfigure the device with actual por defaults from eeprom. it has the same effect on the registers as a por. table 3-10. por defaults data structure offset value 00h ? 07h output port 0-7 08h ? 0fh interrupt mask port 0-7 10h ? 17h select pwm port 0-7 18h ? 1fh inversion port 0-7 20h ? 27h pin direction port 0-7 28h resistive pull up drive mode port 0 29h resistive pull down drive mode port 0 2ah open drain high drive mode port 0 2bh open drain low drive mode port 0 2ch strong drive drive mode port 0 2dh slow strong drive drive mode port 0 2eh high impedance drive mode port 0 2fh ? 35h drive modes port 1 36h ? 3ch drive modes port 2 3dh ? 43h drive modes port 3 44h ? 4ah drive modes port 4 4bh ? 51h drive modes port 5 52h ? 58h drive modes port 6 59h ? 5fh drive modes port 7 60h config setting pwm0 61h period setting pwm0 62h pulse width setting pwm0 63h ? 65h pwm1 settings ?? 8dh ? 8fh pwm15 settings 90h divider 91h enable 92h crc
august 17, 2005 document no. 38-12036 rev. *a 16 4. electrical specifications this chapter presents the dc and ac electrical specifications of the cy8c95xx device. for the most up to date electrical specif ica- tions, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. specifications are valid for -40 o c t a 85 o c and t j 100 o c, except where noted. the following table lists the units of measure that are used in this chapter. 4.1 absolute maximum ratings table 4-1: units of measure symbol unit of measure symbol unit of measure o c degree celsius ma milli-ampere khz kilohertz na nanoampere mhz megahertz ns nanosecond s microsecond pf picofarad v microvolts v volts vrms microvolts root-mean-square table 4-2: absolute maximum ratings symbol description min typ max units notes t stg storage temperature -45 ? +100 o c higher storage temperatures will reduce data retention time. t a ambient temperature with power applied -40 ? +85 o c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tri-state vss - 0.5 ? vdd + 0.5 v i mio maximum current into any port pin -25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch-up current ? ? 200 ma
august 17, 2005 document no. 38-12036 rev. *a 17 cy8c95xx preliminary data sheet 4. electrical specifications 4.2 operating temperature 4.3 dc electrical characteristics 4.3.1 dc chip-level specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 4-3: operating temperature symbol description min typ max units notes t a ambient temperature -40 ? +85 o c t j junction temperature -40 ? +100 o c the temperature rise from ambient to junction is package specific. see ?thermal impedances? on page 23 . the user must limit the power con- sumption to comply with this requirement. table 4-4: cy8c9520 dc chip-level specifications symbol description min typ max units notes vdd supply voltage 3.00 ? 5.25 v i dd supply current vdd 5v ? 3.8 5 ma conditions are 5.0v, t a = 25 o c, ioh = 0. i dd3 supply current vdd 3.3v ? 2.3 3 ma conditions are 3.3v, t a = 25 o c, ioh = 0. table 4-5: cy8c9540 dc chip-level specifications symbol description min typ max units notes vdd supply voltage 3.00 ? 5.25 v i dd supply current vdd 5v ? 6 9 ma conditions are 5.0v, t a = 25 o c, ioh = 0. i dd3 supply current vdd 3.3v ? 3.3 6 ma conditions are 3.3v, t a = 25 o c, ioh = 0. table 4-6: cy8c9560 dc chip-level specifications symbol description min typ max units notes vdd supply voltage 3.00 ? 5.25 v i dd supply current vdd 5v ? 15 25 ma conditions are 5.0v, t a = 25 o c, ioh = 0. i dd3 supply current vdd 3.3v ? 5 9 ma conditions are 3.3v, t a = 25 o c, ioh = 0.
august 17, 2005 document no. 38-12036 rev. *a 18 cy8c95xx preliminary data sheet 4. electrical specifications 4.3.2 dc programming specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. 4.3.3 dc general purpose i/o specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 4-7. dc programming specifications symbol description min typ max units notes flash enpb flash (eeprom) endurance (per block) 50,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) 1 1. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? yea rs table 4-8: dc gpio specifications symbol description min typ max units notes v oh high output level vdd - 1.0 ? ? v ioh = 10 ma for any one pin, vdd = 4.75 to 5.25v. 40 ma maximum combined ioh for gport0; gport2_bit3; gport3; gport5_bit2, 3, 6, 7; gport6. 40 ma maximum combined ioh for gport1; gport2_bit0, 1, 2; gport4; gport5_bit0, 1, 4, 5; gport7. 80 ma maximum combined ioh. v ol low output level ? ? 0.75 v iol = 25 ma for any one pin, vdd = 4.75 to 5.25v. 100 ma maximum combined iol for gport0; gport2_bit3; gport3; gport5_bit2, 3, 6, 7; gport6. 100 ma maximum combined iol for gport1; gport2_bit0, 1, 2; gport4; gport5_bit0, 1, 4, 5; gport7. 200 ma maximum combined iol. v il input low level ? ? 0.8 v vdd = 3.0 to 5.5. v ih input high level 2.1 ? v vdd = 3.0 to 5.5. i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 o c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 o c.
august 17, 2005 document no. 38-12036 rev. *a 19 cy8c95xx preliminary data sheet 4. electrical specifications 4.4 ac electrical characteristics 4.4.1 ac general purpose i/o specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. figure 4-1. gpio timing diagram 4.4.2 ac pwm output jitter specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. table 4-9: ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns vdd = 4.75 to 5.25v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns vdd = 4.75 to 5.25v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns vdd = 3 to 5.25v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns vdd = 3 to 5.25v, 10% - 90% table 4-10: ac pwm output jitter specifications symbol description min typ max units notes jitter24mhzpwm 24 mhz-based pwm peak-to-peak period jitter ? 0.1 1.5 % 24 mhz, 1.5 mhz, 93.75khz and 367.6 hz (programmable) sources. jitter32khzpwm 32 khz-based pwm peak-to-peak period jitter ? 2.5 5.0 % 32 khz clock source. tfallf tfalls trisef tri se s 90% 10% gpio pin output voltage
august 17, 2005 document no. 38-12036 rev. *a 20 cy8c95xx preliminary data sheet 4. electrical specifications 4.4.3 ac i 2 c specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. figure 4-2. definition for timing for fast/standard mode on the i 2 c bus table 4-11: ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c set-up time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data set-up time 250 ? 100 3 ?ns t sustoi2c set-up time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ?050ns sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c
august 17, 2005 document no. 38-12036 rev. *a 21 5. packaging information this chapter illustrates the packaging specifications for the cy8c95xx device, along with the thermal impedances for each packa ge, the typical package capacitance on crystal pins, and the solder reflow peak temperature. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress.com/support/link.cfm?mr=poddim . 5.1 packaging dimensions figure 5-1. 28-lead (210-mil) ssop 51-85079 - *c
august 17, 2005 document no. 38-12036 rev. *a 22 cy8c95xx preliminary data sheet 5. packaging information figure 5-2. 48-lead (300-mil) ssop figure 5-3. 100-lead (14 x 14 x 1.0 mm) tqfp 51-85061 - *c 51-85048 - *b
august 17, 2005 document no. 38-12036 rev. *a 23 cy8c95xx preliminary data sheet 5. packaging information 5.2 thermal impedances 5.3 solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. table 5-1. thermal impedances per package package typical ja * 28 ssop 101 o c/w 48 ssop 69 o c/w 100 tqfp 48 o c/w * t j = t a + power x ja table 5-2. solder reflow peak temperature package minimum peak temperature* maximum peak temperature 28 ssop 240 o c 260 o c 48 ssop 220 o c 260 o c 100 tqfp 220 o c 260 o c *higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220+/-5 o c with sn-pb or 245+/-5 o c with sn-ag-cu paste. refer to the solder manufacturer specifications.
august 17, 2005 document no. 38-12036 rev. *a 24 6. ordering information the following table lists the cy8c95xx device?s key package features and ordering codes. a definition of the ordering number co de is presented below. 6.1 ordering code definitions table 6-1. cy8c95xx device key features and ordering information package ordering code eeprom (bytes) temperature range pwm sources configurable i/o pins 28 pin (210 mil) ssop CY8C9520-24PVXI 3k -40c to +85c 4 20 28 pin (210 mil) ssop (tape and reel) CY8C9520-24PVXIt 3k -40c to +85c 4 20 48 pin (300 mil) ssop cy8c9540-24pvxi 11k -40c to +85c 8 40 48 pin (300 mil) ssop (tape and reel) cy8c9540-24pvxit 11k -40c to +85c 8 40 100 pin tqfp cy8c9560-24axi 27k -40c to +85c 16 60 100 pin tqfp (tape and reel) cy8c9560-24axit 27k -40c to +85c 16 60 c y 8 c 9 xxx-spxx package type: thermal rating: px = pdip pb-free c = commercial sx = soic pb-free i = industrial pvx = ssop pb-free e = extended lfx = mlf pb-free ax = tqfp pb-free speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = cypress microsystems company id: cy = cypress
august 17, 2005 ? cypress semiconductor corp. 2005 ? document no. 38-12036 rev. *a 25 7. sales and service information to obtain information about cypress semiconductor or sales and technical support, reference the following informationt. cypress semiconductor 7.1 revision history 7.2 copyrights and code protection copyrights ? cypress semiconductor corp. 2005. all rights reserved. psoc?, psoc designer?, programmable system-on-chip?, and psoc express ? are trademarks of cypress semiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corp orations. the information contained herein is subject to change without notice. cypress semiconductor assumes no responsibility for the u se of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license under patent or other rights. cypress semi conductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in s ignificant injury to the user. the inclusion of cypress semiconductor products in life-support systems applicatio n implies that the manufacturer assumes all risk of such use a nd in doing so indemnifies cypress semiconductor against all charges. cypress semiconductor products are not warranted nor intended to be used for medical, life-s upport, life-saving, critical control or safety applications, unless pursuant to an express written agreement with cypress semiconductor. flash code protection note the following details of the flash code protection features on cypress semiconductor psoc-related devices. cypress microsystems products meet the specifications contained in their particular cypress semiconductor data sheets. cypress semiconductor believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. there may be m ethods, unknown to cypress semiconduc- tor, that can breach the code protection features. any of these methods, to our knowledge, would be dishonest and possibly ille gal. neither cypress semiconductor nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaran teeing the product as "unbreakable." cypress semiconductor is willing to work with the customer who is concerned about the integrity of their code. code protection is constantly evolving. we at cypress semiconductor are committed to continuously improving the code protection features of our products. 2700 162nd street sw, building d lynnwood, wa 98087 phone: 800.669.0557 facsimile: 425.787.4641 web sites: company information ? http://www.cypress.com sales ? http://www.cypress.com/aboutus/sales_locations.cfm technical support ? http://www.cypress.com/support/login.cfm table 7-1. cy8c95xx data sheet revision history document title: cy8c95xx preliminary data sheet document number: 38-12036 revision ecn # issue date origin of change description of change ** 346754 see ecn hmt new silicon, document. *a 392484 see ecn hmt correct pin 79 on the tqfp. add ac pwm output jitter spec. table. upgrade to cy perform logo and update zip code and trademarks. distribution : external/public posting : none

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